// ----------------------------------------------------------------------
//  Copyright (c) 2008-2010 Marvell Semiconductor
//  All Rights Reserved
// ----------------------------------------------------------------------
#ifndef __MSEC_TEST_H
#define __MSEC_TEST_H


#define REV_A0       0
#define REV_A0_UP    1
#define  PROD_1540L  2

#define NUM_OF_MAC_STAT 0x20
#define Max_List_Num 16

#define bit_clr bit_clear

typedef enum {
MX_SEC_A0_IGR_HIT_E0,
MX_SEC_A0_IGR_HIT_E1,
MX_SEC_A0_IGR_HIT_E2,
MX_SEC_A0_IGR_HIT_E3,
MX_SEC_A0_IGR_HIT_E4,
MX_SEC_A0_IGR_HIT_E5,
MX_SEC_A0_IGR_HIT_E6,
MX_SEC_A0_IGR_HIT_E7,
MX_SEC_A0_IGR_OK_E0,
MX_SEC_A0_IGR_OK_E1,
MX_SEC_A0_IGR_OK_E2,
MX_SEC_A0_IGR_OK_E3,
MX_SEC_A0_IGR_OK_E4,
MX_SEC_A0_IGR_OK_E5,
MX_SEC_A0_IGR_OK_E6,
MX_SEC_A0_IGR_OK_E7,
MX_SEC_A0_IGR_UNCHK_E0,
MX_SEC_A0_IGR_UNCHK_E1,
MX_SEC_A0_IGR_UNCHK_E2,
MX_SEC_A0_IGR_UNCHK_E3,
MX_SEC_A0_IGR_UNCHK_E4,
MX_SEC_A0_IGR_UNCHK_E5,
MX_SEC_A0_IGR_UNCHK_E6,
MX_SEC_A0_IGR_UNCHK_E7,
MX_SEC_A0_IGR_DELAY_E0,
MX_SEC_A0_IGR_DELAY_E1,
MX_SEC_A0_IGR_DELAY_E2,
MX_SEC_A0_IGR_DELAY_E3,
MX_SEC_A0_IGR_DELAY_E4,
MX_SEC_A0_IGR_DELAY_E5,
MX_SEC_A0_IGR_DELAY_E6,
MX_SEC_A0_IGR_DELAY_E7,
MX_SEC_A0_IGR_LATE_E0,
MX_SEC_A0_IGR_LATE_E1,
MX_SEC_A0_IGR_LATE_E2,
MX_SEC_A0_IGR_LATE_E3,
MX_SEC_A0_IGR_LATE_E4,
MX_SEC_A0_IGR_LATE_E5,
MX_SEC_A0_IGR_LATE_E6,
MX_SEC_A0_IGR_LATE_E7,
MX_SEC_A0_IGR_INVLD_E0,
MX_SEC_A0_IGR_INVLD_E1,
MX_SEC_A0_IGR_INVLD_E2,
MX_SEC_A0_IGR_INVLD_E3,
MX_SEC_A0_IGR_INVLD_E4,
MX_SEC_A0_IGR_INVLD_E5,
MX_SEC_A0_IGR_INVLD_E6,
MX_SEC_A0_IGR_INVLD_E7,
MX_SEC_A0_IGR_NOTVLD_E0,
MX_SEC_A0_IGR_NOTVLD_E1,
MX_SEC_A0_IGR_NOTVLD_E2,
MX_SEC_A0_IGR_NOTVLD_E3,
MX_SEC_A0_IGR_NOTVLD_E4,
MX_SEC_A0_IGR_NOTVLD_E5,
MX_SEC_A0_IGR_NOTVLD_E6,
MX_SEC_A0_IGR_NOTVLD_E7,
MX_SEC_A0_EGR_PKT_PROT_E0,
MX_SEC_A0_EGR_PKT_PROT_E1,
MX_SEC_A0_EGR_PKT_PROT_E2,
MX_SEC_A0_EGR_PKT_PROT_E3,
MX_SEC_A0_EGR_PKT_PROT_E4,
MX_SEC_A0_EGR_PKT_PROT_E5,
MX_SEC_A0_EGR_PKT_PROT_E6,
MX_SEC_A0_EGR_PKT_PROT_E7,
MX_SEC_A0_EGR_PKT_ENC_E0,
MX_SEC_A0_EGR_PKT_ENC_E1,
MX_SEC_A0_EGR_PKT_ENC_E2,
MX_SEC_A0_EGR_PKT_ENC_E3,
MX_SEC_A0_EGR_PKT_ENC_E4,
MX_SEC_A0_EGR_PKT_ENC_E5,
MX_SEC_A0_EGR_PKT_ENC_E6,
MX_SEC_A0_EGR_PKT_ENC_E7,
MX_SEC_A0_EGR_HIT_E0,
MX_SEC_A0_EGR_HIT_E1,
MX_SEC_A0_EGR_HIT_E2,
MX_SEC_A0_EGR_HIT_E3,
MX_SEC_A0_EGR_HIT_E4,
MX_SEC_A0_EGR_HIT_E5,
MX_SEC_A0_EGR_HIT_E6,
MX_SEC_A0_EGR_HIT_E7,
MX_SEC_A0_IGR_OCT_VAL,
MX_SEC_A0_IGR_OCT_DEC,
MX_SEC_A0_IGR_UNTAG,
MX_SEC_A0_IGR_NOTAG,
MX_SEC_A0_IGR_BADTAG,
MX_SEC_A0_IGR_UNKSCI,
MX_SEC_A0_IGR_NOSCI,
MX_SEC_A0_IGR_UNUSSA,
MX_SEC_A0_IGR_NOUSSA,
MX_SEC_A0_IGR_OCT_TOT,
MX_SEC_A0_EGR_OCT_PROT,
MX_SEC_A0_EGR_OCT_ENC,
MX_SEC_A0_EGR_OCT_TOTAL,
MX_SEC_A0_IGR_MISS,
MX_SEC_A0_EGR_MISS,
MX_SEC_A0_IGR_REDIR
} MACSEC_A0_ST_NAME;

typedef enum {
MX_SEC_A0_UP_IGR_HIT_E0,
MX_SEC_A0_UP_IGR_HIT_E1,
MX_SEC_A0_UP_IGR_HIT_E2,
MX_SEC_A0_UP_IGR_HIT_E3,
MX_SEC_A0_UP_IGR_HIT_E4,
MX_SEC_A0_UP_IGR_HIT_E5,
MX_SEC_A0_UP_IGR_HIT_E6,
MX_SEC_A0_UP_IGR_HIT_E7,
MX_SEC_A0_UP_IGR_HIT_E8,
MX_SEC_A0_UP_IGR_HIT_E9,
MX_SEC_A0_UP_IGR_HIT_E10,
MX_SEC_A0_UP_IGR_HIT_E11,
MX_SEC_A0_UP_IGR_HIT_E12,
MX_SEC_A0_UP_IGR_HIT_E13,
MX_SEC_A0_UP_IGR_HIT_E14,
MX_SEC_A0_UP_IGR_HIT_E15,
MX_SEC_A0_UP_IGR_OK_E0,
MX_SEC_A0_UP_IGR_OK_E1,
MX_SEC_A0_UP_IGR_OK_E2,
MX_SEC_A0_UP_IGR_OK_E3,
MX_SEC_A0_UP_IGR_OK_E4,
MX_SEC_A0_UP_IGR_OK_E5,
MX_SEC_A0_UP_IGR_OK_E6,
MX_SEC_A0_UP_IGR_OK_E7,
MX_SEC_A0_UP_IGR_OK_E8,
MX_SEC_A0_UP_IGR_OK_E9,
MX_SEC_A0_UP_IGR_OK_E10,
MX_SEC_A0_UP_IGR_OK_E11,
MX_SEC_A0_UP_IGR_OK_E12,
MX_SEC_A0_UP_IGR_OK_E13,
MX_SEC_A0_UP_IGR_OK_E14,
MX_SEC_A0_UP_IGR_OK_E15,
MX_SEC_A0_UP_IGR_UNCHK_E0,
MX_SEC_A0_UP_IGR_UNCHK_E1,
MX_SEC_A0_UP_IGR_UNCHK_E2,
MX_SEC_A0_UP_IGR_UNCHK_E3,
MX_SEC_A0_UP_IGR_UNCHK_E4,
MX_SEC_A0_UP_IGR_UNCHK_E5,
MX_SEC_A0_UP_IGR_UNCHK_E6,
MX_SEC_A0_UP_IGR_UNCHK_E7,
MX_SEC_A0_UP_IGR_UNCHK_E8,
MX_SEC_A0_UP_IGR_UNCHK_E9,
MX_SEC_A0_UP_IGR_UNCHK_E10,
MX_SEC_A0_UP_IGR_UNCHK_E11,
MX_SEC_A0_UP_IGR_UNCHK_E12,
MX_SEC_A0_UP_IGR_UNCHK_E13,
MX_SEC_A0_UP_IGR_UNCHK_E14,
MX_SEC_A0_UP_IGR_UNCHK_E15,
MX_SEC_A0_UP_IGR_DELAY_E0,
MX_SEC_A0_UP_IGR_DELAY_E1,
MX_SEC_A0_UP_IGR_DELAY_E2,
MX_SEC_A0_UP_IGR_DELAY_E3,
MX_SEC_A0_UP_IGR_DELAY_E4,
MX_SEC_A0_UP_IGR_DELAY_E5,
MX_SEC_A0_UP_IGR_DELAY_E6,
MX_SEC_A0_UP_IGR_DELAY_E7,
MX_SEC_A0_UP_IGR_DELAY_E8,
MX_SEC_A0_UP_IGR_DELAY_E9,
MX_SEC_A0_UP_IGR_DELAY_E10,
MX_SEC_A0_UP_IGR_DELAY_E11,
MX_SEC_A0_UP_IGR_DELAY_E12,
MX_SEC_A0_UP_IGR_DELAY_E13,
MX_SEC_A0_UP_IGR_DELAY_E14,
MX_SEC_A0_UP_IGR_DELAY_E15,
MX_SEC_A0_UP_IGR_LATE_E0,
MX_SEC_A0_UP_IGR_LATE_E1,
MX_SEC_A0_UP_IGR_LATE_E2,
MX_SEC_A0_UP_IGR_LATE_E3,
MX_SEC_A0_UP_IGR_LATE_E4,
MX_SEC_A0_UP_IGR_LATE_E5,
MX_SEC_A0_UP_IGR_LATE_E6,
MX_SEC_A0_UP_IGR_LATE_E7,
MX_SEC_A0_UP_IGR_LATE_E8,
MX_SEC_A0_UP_IGR_LATE_E9,
MX_SEC_A0_UP_IGR_LATE_E10,
MX_SEC_A0_UP_IGR_LATE_E11,
MX_SEC_A0_UP_IGR_LATE_E12,
MX_SEC_A0_UP_IGR_LATE_E13,
MX_SEC_A0_UP_IGR_LATE_E14,
MX_SEC_A0_UP_IGR_LATE_E15,
MX_SEC_A0_UP_IGR_INVLD_E0,
MX_SEC_A0_UP_IGR_INVLD_E1,
MX_SEC_A0_UP_IGR_INVLD_E2,
MX_SEC_A0_UP_IGR_INVLD_E3,
MX_SEC_A0_UP_IGR_INVLD_E4,
MX_SEC_A0_UP_IGR_INVLD_E5,
MX_SEC_A0_UP_IGR_INVLD_E6,
MX_SEC_A0_UP_IGR_INVLD_E7,
MX_SEC_A0_UP_IGR_INVLD_E8,
MX_SEC_A0_UP_IGR_INVLD_E9,
MX_SEC_A0_UP_IGR_INVLD_E10,
MX_SEC_A0_UP_IGR_INVLD_E11,
MX_SEC_A0_UP_IGR_INVLD_E12,
MX_SEC_A0_UP_IGR_INVLD_E13,
MX_SEC_A0_UP_IGR_INVLD_E14,
MX_SEC_A0_UP_IGR_INVLD_E15,
MX_SEC_A0_UP_IGR_NOTVLD_E0,
MX_SEC_A0_UP_IGR_NOTVLD_E1,
MX_SEC_A0_UP_IGR_NOTVLD_E2,
MX_SEC_A0_UP_IGR_NOTVLD_E3,
MX_SEC_A0_UP_IGR_NOTVLD_E4,
MX_SEC_A0_UP_IGR_NOTVLD_E5,
MX_SEC_A0_UP_IGR_NOTVLD_E6,
MX_SEC_A0_UP_IGR_NOTVLD_E7,
MX_SEC_A0_UP_IGR_NOTVLD_E8,
MX_SEC_A0_UP_IGR_NOTVLD_E9,
MX_SEC_A0_UP_IGR_NOTVLD_E10,
MX_SEC_A0_UP_IGR_NOTVLD_E11,
MX_SEC_A0_UP_IGR_NOTVLD_E12,
MX_SEC_A0_UP_IGR_NOTVLD_E13,
MX_SEC_A0_UP_IGR_NOTVLD_E14,
MX_SEC_A0_UP_IGR_NOTVLD_E15,
MX_SEC_A0_UP_EGR_PKT_PROT_E0,
MX_SEC_A0_UP_EGR_PKT_PROT_E1,
MX_SEC_A0_UP_EGR_PKT_PROT_E2,
MX_SEC_A0_UP_EGR_PKT_PROT_E3,
MX_SEC_A0_UP_EGR_PKT_PROT_E4,
MX_SEC_A0_UP_EGR_PKT_PROT_E5,
MX_SEC_A0_UP_EGR_PKT_PROT_E6,
MX_SEC_A0_UP_EGR_PKT_PROT_E7,
MX_SEC_A0_UP_EGR_PKT_PROT_E8,
MX_SEC_A0_UP_EGR_PKT_PROT_E9,
MX_SEC_A0_UP_EGR_PKT_PROT_E10,
MX_SEC_A0_UP_EGR_PKT_PROT_E11,
MX_SEC_A0_UP_EGR_PKT_PROT_E12,
MX_SEC_A0_UP_EGR_PKT_PROT_E13,
MX_SEC_A0_UP_EGR_PKT_PROT_E14,
MX_SEC_A0_UP_EGR_PKT_PROT_E15,
MX_SEC_A0_UP_EGR_PKT_ENC_E0,
MX_SEC_A0_UP_EGR_PKT_ENC_E1,
MX_SEC_A0_UP_EGR_PKT_ENC_E2,
MX_SEC_A0_UP_EGR_PKT_ENC_E3,
MX_SEC_A0_UP_EGR_PKT_ENC_E4,
MX_SEC_A0_UP_EGR_PKT_ENC_E5,
MX_SEC_A0_UP_EGR_PKT_ENC_E6,
MX_SEC_A0_UP_EGR_PKT_ENC_E7,
MX_SEC_A0_UP_EGR_PKT_ENC_E8,
MX_SEC_A0_UP_EGR_PKT_ENC_E9,
MX_SEC_A0_UP_EGR_PKT_ENC_E10,
MX_SEC_A0_UP_EGR_PKT_ENC_E11,
MX_SEC_A0_UP_EGR_PKT_ENC_E12,
MX_SEC_A0_UP_EGR_PKT_ENC_E13,
MX_SEC_A0_UP_EGR_PKT_ENC_E14,
MX_SEC_A0_UP_EGR_PKT_ENC_E15,
MX_SEC_A0_UP_EGR_HIT_E0,
MX_SEC_A0_UP_EGR_HIT_E1,
MX_SEC_A0_UP_EGR_HIT_E2,
MX_SEC_A0_UP_EGR_HIT_E3,
MX_SEC_A0_UP_EGR_HIT_E4,
MX_SEC_A0_UP_EGR_HIT_E5,
MX_SEC_A0_UP_EGR_HIT_E6,
MX_SEC_A0_UP_EGR_HIT_E7,
MX_SEC_A0_UP_EGR_HIT_E8,
MX_SEC_A0_UP_EGR_HIT_E9,
MX_SEC_A0_UP_EGR_HIT_E10,
MX_SEC_A0_UP_EGR_HIT_E11,
MX_SEC_A0_UP_EGR_HIT_E12,
MX_SEC_A0_UP_EGR_HIT_E13,
MX_SEC_A0_UP_EGR_HIT_E14,
MX_SEC_A0_UP_EGR_HIT_E15,
MX_SEC_A0_UP_IGR_OCT_VAL,
MX_SEC_A0_UP_IGR_OCT_DEC,
MX_SEC_A0_UP_IGR_UNTAG,
MX_SEC_A0_UP_IGR_NOTAG,
MX_SEC_A0_UP_IGR_BADTAG,
MX_SEC_A0_UP_IGR_UNKSCI,
MX_SEC_A0_UP_IGR_NOSCI,
MX_SEC_A0_UP_IGR_UNUSSA,
MX_SEC_A0_UP_IGR_NOUSSA,
MX_SEC_A0_UP_IGR_OCT_TOT,
MX_SEC_A0_UP_EGR_OCT_PROT,
MX_SEC_A0_UP_EGR_OCT_ENC,
MX_SEC_A0_UP_EGR_OCT_TOTAL,
MX_SEC_A0_UP_IGR_MISS,
MX_SEC_A0_UP_EGR_MISS,
MX_SEC_A0_UP_IGR_REDIR
} MACSEC_A0_UP_ST_NAME;

typedef enum {
MX_SEC_1540_IGR_HIT_E0,
MX_SEC_1540_IGR_HIT_E1,
MX_SEC_1540_IGR_HIT_E2,
MX_SEC_1540_IGR_HIT_E3,
MX_SEC_1540_IGR_HIT_E4,
MX_SEC_1540_IGR_HIT_E5,
MX_SEC_1540_IGR_HIT_E6,
MX_SEC_1540_IGR_HIT_E7,
MX_SEC_1540_IGR_HIT_E8,
MX_SEC_1540_IGR_HIT_E9,
MX_SEC_1540_IGR_HIT_E10,
MX_SEC_1540_IGR_HIT_E11,
MX_SEC_1540_IGR_HIT_E12,
MX_SEC_1540_IGR_HIT_E13,
MX_SEC_1540_IGR_HIT_E14,
MX_SEC_1540_IGR_HIT_E15,
MX_SEC_1540_IGR_HIT_E16,
MX_SEC_1540_IGR_HIT_E17,
MX_SEC_1540_IGR_HIT_E18,
MX_SEC_1540_IGR_HIT_E19,
MX_SEC_1540_IGR_HIT_E20,
MX_SEC_1540_IGR_HIT_E21,
MX_SEC_1540_IGR_HIT_E22,
MX_SEC_1540_IGR_HIT_E23,
MX_SEC_1540_IGR_HIT_E24,
MX_SEC_1540_IGR_HIT_E25,
MX_SEC_1540_IGR_HIT_E26,
MX_SEC_1540_IGR_HIT_E27,
MX_SEC_1540_IGR_HIT_E28,
MX_SEC_1540_IGR_HIT_E29,
MX_SEC_1540_IGR_HIT_E30,
MX_SEC_1540_IGR_HIT_E31,
MX_SEC_1540_IGR_OK_E0,
MX_SEC_1540_IGR_OK_E1,
MX_SEC_1540_IGR_OK_E2,
MX_SEC_1540_IGR_OK_E3,
MX_SEC_1540_IGR_OK_E4,
MX_SEC_1540_IGR_OK_E5,
MX_SEC_1540_IGR_OK_E6,
MX_SEC_1540_IGR_OK_E7,
MX_SEC_1540_IGR_OK_E8,
MX_SEC_1540_IGR_OK_E9,
MX_SEC_1540_IGR_OK_E10,
MX_SEC_1540_IGR_OK_E11,
MX_SEC_1540_IGR_OK_E12,
MX_SEC_1540_IGR_OK_E13,
MX_SEC_1540_IGR_OK_E14,
MX_SEC_1540_IGR_OK_E15,
MX_SEC_1540_IGR_OK_E16,
MX_SEC_1540_IGR_OK_E17,
MX_SEC_1540_IGR_OK_E18,
MX_SEC_1540_IGR_OK_E19,
MX_SEC_1540_IGR_OK_E20,
MX_SEC_1540_IGR_OK_E21,
MX_SEC_1540_IGR_OK_E22,
MX_SEC_1540_IGR_OK_E23,
MX_SEC_1540_IGR_OK_E24,
MX_SEC_1540_IGR_OK_E25,
MX_SEC_1540_IGR_OK_E26,
MX_SEC_1540_IGR_OK_E27,
MX_SEC_1540_IGR_OK_E28,
MX_SEC_1540_IGR_OK_E29,
MX_SEC_1540_IGR_OK_E30,
MX_SEC_1540_IGR_OK_E31,
MX_SEC_1540_IGR_UNCHK_E0,
MX_SEC_1540_IGR_UNCHK_E1,
MX_SEC_1540_IGR_UNCHK_E2,
MX_SEC_1540_IGR_UNCHK_E3,
MX_SEC_1540_IGR_UNCHK_E4,
MX_SEC_1540_IGR_UNCHK_E5,
MX_SEC_1540_IGR_UNCHK_E6,
MX_SEC_1540_IGR_UNCHK_E7,
MX_SEC_1540_IGR_UNCHK_E8,
MX_SEC_1540_IGR_UNCHK_E9,
MX_SEC_1540_IGR_UNCHK_E10,
MX_SEC_1540_IGR_UNCHK_E11,
MX_SEC_1540_IGR_UNCHK_E12,
MX_SEC_1540_IGR_UNCHK_E13,
MX_SEC_1540_IGR_UNCHK_E14,
MX_SEC_1540_IGR_UNCHK_E15,
MX_SEC_1540_IGR_UNCHK_E16,
MX_SEC_1540_IGR_UNCHK_E17,
MX_SEC_1540_IGR_UNCHK_E18,
MX_SEC_1540_IGR_UNCHK_E19,
MX_SEC_1540_IGR_UNCHK_E20,
MX_SEC_1540_IGR_UNCHK_E21,
MX_SEC_1540_IGR_UNCHK_E22,
MX_SEC_1540_IGR_UNCHK_E23,
MX_SEC_1540_IGR_UNCHK_E24,
MX_SEC_1540_IGR_UNCHK_E25,
MX_SEC_1540_IGR_UNCHK_E26,
MX_SEC_1540_IGR_UNCHK_E27,
MX_SEC_1540_IGR_UNCHK_E28,
MX_SEC_1540_IGR_UNCHK_E29,
MX_SEC_1540_IGR_UNCHK_E30,
MX_SEC_1540_IGR_UNCHK_E31,
MX_SEC_1540_IGR_DELAY_E0,
MX_SEC_1540_IGR_DELAY_E1,
MX_SEC_1540_IGR_DELAY_E2,
MX_SEC_1540_IGR_DELAY_E3,
MX_SEC_1540_IGR_DELAY_E4,
MX_SEC_1540_IGR_DELAY_E5,
MX_SEC_1540_IGR_DELAY_E6,
MX_SEC_1540_IGR_DELAY_E7,
MX_SEC_1540_IGR_DELAY_E8,
MX_SEC_1540_IGR_DELAY_E9,
MX_SEC_1540_IGR_DELAY_E10,
MX_SEC_1540_IGR_DELAY_E11,
MX_SEC_1540_IGR_DELAY_E12,
MX_SEC_1540_IGR_DELAY_E13,
MX_SEC_1540_IGR_DELAY_E14,
MX_SEC_1540_IGR_DELAY_E15,
MX_SEC_1540_IGR_DELAY_E16,
MX_SEC_1540_IGR_DELAY_E17,
MX_SEC_1540_IGR_DELAY_E18,
MX_SEC_1540_IGR_DELAY_E19,
MX_SEC_1540_IGR_DELAY_E20,
MX_SEC_1540_IGR_DELAY_E21,
MX_SEC_1540_IGR_DELAY_E22,
MX_SEC_1540_IGR_DELAY_E23,
MX_SEC_1540_IGR_DELAY_E24,
MX_SEC_1540_IGR_DELAY_E25,
MX_SEC_1540_IGR_DELAY_E26,
MX_SEC_1540_IGR_DELAY_E27,
MX_SEC_1540_IGR_DELAY_E28,
MX_SEC_1540_IGR_DELAY_E29,
MX_SEC_1540_IGR_DELAY_E30,
MX_SEC_1540_IGR_DELAY_E31,
MX_SEC_1540_IGR_LATE_E0,
MX_SEC_1540_IGR_LATE_E1,
MX_SEC_1540_IGR_LATE_E2,
MX_SEC_1540_IGR_LATE_E3,
MX_SEC_1540_IGR_LATE_E4,
MX_SEC_1540_IGR_LATE_E5,
MX_SEC_1540_IGR_LATE_E6,
MX_SEC_1540_IGR_LATE_E7,
MX_SEC_1540_IGR_LATE_E8,
MX_SEC_1540_IGR_LATE_E9,
MX_SEC_1540_IGR_LATE_E10,
MX_SEC_1540_IGR_LATE_E11,
MX_SEC_1540_IGR_LATE_E12,
MX_SEC_1540_IGR_LATE_E13,
MX_SEC_1540_IGR_LATE_E14,
MX_SEC_1540_IGR_LATE_E15,
MX_SEC_1540_IGR_LATE_E16,
MX_SEC_1540_IGR_LATE_E17,
MX_SEC_1540_IGR_LATE_E18,
MX_SEC_1540_IGR_LATE_E19,
MX_SEC_1540_IGR_LATE_E20,
MX_SEC_1540_IGR_LATE_E21,
MX_SEC_1540_IGR_LATE_E22,
MX_SEC_1540_IGR_LATE_E23,
MX_SEC_1540_IGR_LATE_E24,
MX_SEC_1540_IGR_LATE_E25,
MX_SEC_1540_IGR_LATE_E26,
MX_SEC_1540_IGR_LATE_E27,
MX_SEC_1540_IGR_LATE_E28,
MX_SEC_1540_IGR_LATE_E29,
MX_SEC_1540_IGR_LATE_E30,
MX_SEC_1540_IGR_LATE_E31,
MX_SEC_1540_IGR_INVLD_E0,
MX_SEC_1540_IGR_INVLD_E1,
MX_SEC_1540_IGR_INVLD_E2,
MX_SEC_1540_IGR_INVLD_E3,
MX_SEC_1540_IGR_INVLD_E4,
MX_SEC_1540_IGR_INVLD_E5,
MX_SEC_1540_IGR_INVLD_E6,
MX_SEC_1540_IGR_INVLD_E7,
MX_SEC_1540_IGR_INVLD_E8,
MX_SEC_1540_IGR_INVLD_E9,
MX_SEC_1540_IGR_INVLD_E10,
MX_SEC_1540_IGR_INVLD_E11,
MX_SEC_1540_IGR_INVLD_E12,
MX_SEC_1540_IGR_INVLD_E13,
MX_SEC_1540_IGR_INVLD_E14,
MX_SEC_1540_IGR_INVLD_E15,
MX_SEC_1540_IGR_INVLD_E16,
MX_SEC_1540_IGR_INVLD_E17,
MX_SEC_1540_IGR_INVLD_E18,
MX_SEC_1540_IGR_INVLD_E19,
MX_SEC_1540_IGR_INVLD_E20,
MX_SEC_1540_IGR_INVLD_E21,
MX_SEC_1540_IGR_INVLD_E22,
MX_SEC_1540_IGR_INVLD_E23,
MX_SEC_1540_IGR_INVLD_E24,
MX_SEC_1540_IGR_INVLD_E25,
MX_SEC_1540_IGR_INVLD_E26,
MX_SEC_1540_IGR_INVLD_E27,
MX_SEC_1540_IGR_INVLD_E28,
MX_SEC_1540_IGR_INVLD_E29,
MX_SEC_1540_IGR_INVLD_E30,
MX_SEC_1540_IGR_INVLD_E31,
MX_SEC_1540_IGR_NOTVLD_E0,
MX_SEC_1540_IGR_NOTVLD_E1,
MX_SEC_1540_IGR_NOTVLD_E2,
MX_SEC_1540_IGR_NOTVLD_E3,
MX_SEC_1540_IGR_NOTVLD_E4,
MX_SEC_1540_IGR_NOTVLD_E5,
MX_SEC_1540_IGR_NOTVLD_E6,
MX_SEC_1540_IGR_NOTVLD_E7,
MX_SEC_1540_IGR_NOTVLD_E8,
MX_SEC_1540_IGR_NOTVLD_E9,
MX_SEC_1540_IGR_NOTVLD_E10,
MX_SEC_1540_IGR_NOTVLD_E11,
MX_SEC_1540_IGR_NOTVLD_E12,
MX_SEC_1540_IGR_NOTVLD_E13,
MX_SEC_1540_IGR_NOTVLD_E14,
MX_SEC_1540_IGR_NOTVLD_E15,
MX_SEC_1540_IGR_NOTVLD_E16,
MX_SEC_1540_IGR_NOTVLD_E17,
MX_SEC_1540_IGR_NOTVLD_E18,
MX_SEC_1540_IGR_NOTVLD_E19,
MX_SEC_1540_IGR_NOTVLD_E20,
MX_SEC_1540_IGR_NOTVLD_E21,
MX_SEC_1540_IGR_NOTVLD_E22,
MX_SEC_1540_IGR_NOTVLD_E23,
MX_SEC_1540_IGR_NOTVLD_E24,
MX_SEC_1540_IGR_NOTVLD_E25,
MX_SEC_1540_IGR_NOTVLD_E26,
MX_SEC_1540_IGR_NOTVLD_E27,
MX_SEC_1540_IGR_NOTVLD_E28,
MX_SEC_1540_IGR_NOTVLD_E29,
MX_SEC_1540_IGR_NOTVLD_E30,
MX_SEC_1540_IGR_NOTVLD_E31,
MX_SEC_1540_EGR_PKT_PROT_E0,
MX_SEC_1540_EGR_PKT_PROT_E1,
MX_SEC_1540_EGR_PKT_PROT_E2,
MX_SEC_1540_EGR_PKT_PROT_E3,
MX_SEC_1540_EGR_PKT_PROT_E4,
MX_SEC_1540_EGR_PKT_PROT_E5,
MX_SEC_1540_EGR_PKT_PROT_E6,
MX_SEC_1540_EGR_PKT_PROT_E7,
MX_SEC_1540_EGR_PKT_PROT_E8,
MX_SEC_1540_EGR_PKT_PROT_E9,
MX_SEC_1540_EGR_PKT_PROT_E10,
MX_SEC_1540_EGR_PKT_PROT_E11,
MX_SEC_1540_EGR_PKT_PROT_E12,
MX_SEC_1540_EGR_PKT_PROT_E13,
MX_SEC_1540_EGR_PKT_PROT_E14,
MX_SEC_1540_EGR_PKT_PROT_E15,
MX_SEC_1540_EGR_PKT_PROT_E16,
MX_SEC_1540_EGR_PKT_PROT_E17,
MX_SEC_1540_EGR_PKT_PROT_E18,
MX_SEC_1540_EGR_PKT_PROT_E19,
MX_SEC_1540_EGR_PKT_PROT_E20,
MX_SEC_1540_EGR_PKT_PROT_E21,
MX_SEC_1540_EGR_PKT_PROT_E22,
MX_SEC_1540_EGR_PKT_PROT_E23,
MX_SEC_1540_EGR_PKT_PROT_E24,
MX_SEC_1540_EGR_PKT_PROT_E25,
MX_SEC_1540_EGR_PKT_PROT_E26,
MX_SEC_1540_EGR_PKT_PROT_E27,
MX_SEC_1540_EGR_PKT_PROT_E28,
MX_SEC_1540_EGR_PKT_PROT_E29,
MX_SEC_1540_EGR_PKT_PROT_E30,
MX_SEC_1540_EGR_PKT_PROT_E31,
MX_SEC_1540_EGR_PKT_ENC_E0,
MX_SEC_1540_EGR_PKT_ENC_E1,
MX_SEC_1540_EGR_PKT_ENC_E2,
MX_SEC_1540_EGR_PKT_ENC_E3,
MX_SEC_1540_EGR_PKT_ENC_E4,
MX_SEC_1540_EGR_PKT_ENC_E5,
MX_SEC_1540_EGR_PKT_ENC_E6,
MX_SEC_1540_EGR_PKT_ENC_E7,
MX_SEC_1540_EGR_PKT_ENC_E8,
MX_SEC_1540_EGR_PKT_ENC_E9,
MX_SEC_1540_EGR_PKT_ENC_E10,
MX_SEC_1540_EGR_PKT_ENC_E11,
MX_SEC_1540_EGR_PKT_ENC_E12,
MX_SEC_1540_EGR_PKT_ENC_E13,
MX_SEC_1540_EGR_PKT_ENC_E14,
MX_SEC_1540_EGR_PKT_ENC_E15,
MX_SEC_1540_EGR_PKT_ENC_E16,
MX_SEC_1540_EGR_PKT_ENC_E17,
MX_SEC_1540_EGR_PKT_ENC_E18,
MX_SEC_1540_EGR_PKT_ENC_E19,
MX_SEC_1540_EGR_PKT_ENC_E20,
MX_SEC_1540_EGR_PKT_ENC_E21,
MX_SEC_1540_EGR_PKT_ENC_E22,
MX_SEC_1540_EGR_PKT_ENC_E23,
MX_SEC_1540_EGR_PKT_ENC_E24,
MX_SEC_1540_EGR_PKT_ENC_E25,
MX_SEC_1540_EGR_PKT_ENC_E26,
MX_SEC_1540_EGR_PKT_ENC_E27,
MX_SEC_1540_EGR_PKT_ENC_E28,
MX_SEC_1540_EGR_PKT_ENC_E29,
MX_SEC_1540_EGR_PKT_ENC_E30,
MX_SEC_1540_EGR_PKT_ENC_E31,
MX_SEC_1540_EGR_HIT_E0,
MX_SEC_1540_EGR_HIT_E1,
MX_SEC_1540_EGR_HIT_E2,
MX_SEC_1540_EGR_HIT_E3,
MX_SEC_1540_EGR_HIT_E4,
MX_SEC_1540_EGR_HIT_E5,
MX_SEC_1540_EGR_HIT_E6,
MX_SEC_1540_EGR_HIT_E7,
MX_SEC_1540_EGR_HIT_E8,
MX_SEC_1540_EGR_HIT_E9,
MX_SEC_1540_EGR_HIT_E10,
MX_SEC_1540_EGR_HIT_E11,
MX_SEC_1540_EGR_HIT_E12,
MX_SEC_1540_EGR_HIT_E13,
MX_SEC_1540_EGR_HIT_E14,
MX_SEC_1540_EGR_HIT_E15,
MX_SEC_1540_EGR_HIT_E16,
MX_SEC_1540_EGR_HIT_E17,
MX_SEC_1540_EGR_HIT_E18,
MX_SEC_1540_EGR_HIT_E19,
MX_SEC_1540_EGR_HIT_E20,
MX_SEC_1540_EGR_HIT_E21,
MX_SEC_1540_EGR_HIT_E22,
MX_SEC_1540_EGR_HIT_E23,
MX_SEC_1540_EGR_HIT_E24,
MX_SEC_1540_EGR_HIT_E25,
MX_SEC_1540_EGR_HIT_E26,
MX_SEC_1540_EGR_HIT_E27,
MX_SEC_1540_EGR_HIT_E28,
MX_SEC_1540_EGR_HIT_E29,
MX_SEC_1540_EGR_HIT_E30,
MX_SEC_1540_EGR_HIT_E31,
MX_SEC_1540_IGR_OCT_VAL,
MX_SEC_1540_IGR_OCT_DEC,
MX_SEC_1540_IGR_UNTAG,
MX_SEC_1540_IGR_NOTAG,
MX_SEC_1540_IGR_BADTAG,
MX_SEC_1540_IGR_UNKSCI,
MX_SEC_1540_IGR_NOSCI,
MX_SEC_1540_IGR_UNUSSA,
MX_SEC_1540_IGR_NOUSSA,
MX_SEC_1540_IGR_OCT_TOT,
MX_SEC_1540_EGR_OCT_PROT,
MX_SEC_1540_EGR_OCT_ENC,
MX_SEC_1540_EGR_OCT_TOTAL,
MX_SEC_1540_IGR_MISS,
MX_SEC_1540_EGR_MISS,
MX_SEC_1540_IGR_REDIR
} MACSEC_1540_ST_NAME;

typedef enum {
    RxGoodOctLo,
    RxGoodOctHi,
    RxBadOct,
    TxFifoUnder,
    RxUnicast,
    SentDeferred,
    BroadRx,
    MultiRx,
    Fr64,
	Fr65_127,
    Fr128_255,
    Fr256_511,
    Fr512_1023,
    Fr1024_Max,
    GoodTxOctLo,
    GoodTxOctHi,
    TxUnicast,
    ExCol,
    TxMulti,
    TxBroad,
    SentMultiple,
    FCSent,
    FCReceived,
    RxFifoOver,
    Undersize,
    Fragments,
    Oversize,
    Jabber,
    RxError,
    BadCrc,
    Collisions,
    LateCol
} MAC_NAME;

static void madWait (int waitTime)
{
volatile int count=waitTime*100000;
    while (count--);
}








/*! \brief Task to toggle hard reset for olny MacSec Block
 *
 */
void force_macsec_rst (MAD_DEV *ctrl);

/*! \brief Initialize Maxwell Macsec API
 *
 * @return Returns MAD_DEV on success, 0 on failure
 */
MAD_DEV * macsec_api_init (int usbport);

MAD_STATUS msec_clear_mac_stats(MAD_DEV *dev, int mn);

/*! \brief Initialize Maxwell core
 *
 * Brings Maxwell core out of reset and into a basic bypass configuration with all
 * traffic passing through the core.  In this state the core is ready to begin
 * encrypt and decrypt operations.
 * Added work around for all the problems seen so far (09/11/08).
 *
 * @param *dev_ctrl MAD_DEV (Device control - Port Number Information)
 * @param  speed    Indcates port operation speed (2 -> 1000 Mbps, 1 -> 100 Mbps, 0 -> 10 Mbps)
 */
MAD_STATUS macsec_start (MAD_DEV *dev, int speed);
MAD_STATUS msec_shinit (MAD_DEV *dev, int speed, MAD_BOOL duplex);

MAD_STATUS msec_fixed (MAD_DEV *dev);

char * gen_random_hex_octs(int cnt);
char * gen_random_sci(void);
long long gen_random_64_octs(void);

MAD_DEV * initialize_macsec_api(MAD_DEV * devp);

extern MAD_DEV *maddev;

#endif   /* __MSEC_TEST_H */
